The present invention relates to a method of data communication and a system for carrying out the same. More particularly, the invention relates to a method of high-speed data communication and a high-speed data communication system carrying out the method in conjunction with a local area network (LAN).
FIG. 2 is a view of a program structure for use by a data communication system according to the invention. This system permits personal computers and workstations to perform data communication over high-speed transmission routes such as LAN's. This applicant has already filed U.S. Ser. No. 08/079,872 now U.S. Pat. No. 5,797,041 in connection with the above data communication system.
FIG. 2 highlights a buffer constitution showing how data to be communicated is related to buffers that accommodate it in the data communication system. A transmitter 6 and a receiver 7 are connected to a transmission line 13 through which data is exchanged. The transmitter 6 comprises an application program 60, a transmitting program 63 and a communication controller 68. The program 60 is assigned an application buffer 61 that accommodates application data 62. The transmitting program 63 is assigned a data buffer 64 that temporarily holds part 65 of the application data 62, and a head buffer 66 that temporarily stores communication protocol header information 67. The communication controller 68 is assigned a transmitting buffer 69 that temporarily contains frame data 610 made of header information and application data. The application program 60 and transmitting program 63 are placed in a system memory of the transmitter 6 and processed by a system processor thereof. The system memory and system processor of the transmitter 6 are not shown in FIG. 2. The receiver 7 is composed of an application program 70, a receiving program 73 and a communication controller 76. The application program 70 is assigned an application buffer 71 for holding the application data 72 received. The receiving program 73 is assigned a protocol buffer 74 that temporarily stores part 75 of the application data 72. The communication controller 76 is assigned a receiving buffer 77 that temporarily accommodates frame data 78 received. The application program 70 and receiving program 73 are placed in a system memory of the receiver 7 and processed by a system processor thereof. The system memory and system processor of the receiver 7 are not shown in FIG. 2. In FIG. 2, the transmitter 6 divides the application data 62 in the application buffer 61 into pieces and sends them onto the transmission line 13 via the data buffer 64 and transmitting buffer 69. The receiver 7 receives the pieces of data via the receiving buffer 77 and protocol buffer 74 into the application buffer 71 where the pieces are reassembled.
One drawback of this inventor's previous invention is the absence of consideration for the amount to be divided of the application data 62. Also not considered are the locations in which to store data in the buffers involved. If the data starting address boundaries fail to coincide with each other upon data copy between two buffers, it takes time to do the copying therebetween. The result is a drop in performance.
In FIG. 2, the system processor of the transmitter 6 and that of the receiver 7 are a 32-bit processor each, the processors handling data in increments of four bytes. The starting address in each buffer is located so that the address will be an integer multiple of the minimum byte length. That location is called a word boundary. FIG. 3 shows how data is typically moved between buffers. The buffers in FIG. 3 each have the same constitution as that depicted in FIG. 2 and identified by the same reference numerals. Each division in a buffer represents a one-byte address, the addresses getting higher from left to right. Each of the inverted triangles points to a word boundary. The location one byte higher than a given word boundary is called a one-byte boundary; two bytes higher, a two-byte boundary; three bytes higher, a three-byte boundary. In general, the 32-bit processor can read data four bytes at a time from word boundaries in the system memory but cannot gain access to that memory across any word boundary. This means that upon data copy, data may be moved from a copy source to a copy destination simply in increments of four bytes if the word boundaries coincide therebetween; if the word boundaries do not match between the source and the destination, data needs to be moved from one to the other in increments or one or two bytes. In the latter case, the increased number of times the memory is accessed means more time required for the copy operation. FIG. 3 shows an example in which 10 bytes of application data 621 are transmitted first, followed by another 10 bytes of application data 622. The header information is composed of five bytes. Because the starting address of the application data 622 is stored on a two-byte boundary, data is copied from the application buffer 61 to the data buffer 64 in five increments of two bytes each. The header information is copied from the data buffer 64 to the transmitting buffer 69 in two divisions, i.e., four bytes and one byte. Meanwhile, the data is copied from the data buffer 64 to the transmitting buffer 69 in 12 increments of one byte each. The frame data received from the starting address of the receiving buffer 77 via the transmission line 13 is copied in three increments of four bytes each and in three increments of one byte each to the protocol buffer 74. Between the application buffer 71 and the protocol buffer 74, starting address boundaries do not coincide with each other. This requires copying the data from the protocol buffer 74 to the application buffer 71 in 10 increments of one byte each.